Author of the publication

s low power interface with all digital clock multiplier for on-the-fly rate switching.

M. Hossain, K. Kaviani, B. Daly, M. Shirasgaonkar, W. Dettloff, T. Stone, K. Prabhu, B. Tsang, J. Eble, and J. Zerbe. CICC, page 1-4. IEEE, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jared Sonnicksen

Jared Wicks

Jared Miller

Jared Dulmage

Jared Leo

Other publications of authors with the same name

A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on.D. Dunwell, A. Carusone, J. Zerbe, B. Leibowitz, B. Daly, and J. Eble. CICC, page 1-4. IEEE, (2012)A process-independent, 800-MB/s, DRAM byte-wide interface featuring command interleaving and concurrent memory operation.M. Griffin, J. Zerbe, G. Tsang, M. Ching, and C. Portmann. IEEE J. Solid State Circuits, 33 (11): 1741-1751 (1998)Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric.E. Chen, J. Ren, B. Leibowitz, H. Lee, Q. Lin, K. Oh, F. Lambrecht, V. Stojanovic, J. Zerbe, and C. Yang. IEEE J. Solid State Circuits, 43 (9): 2144-2156 (2008)A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching.M. Hossain, K. Kaviani, B. Daly, M. Shirasgaonkar, W. Dettloff, T. Stone, K. Prabhu, B. Tsang, J. Eble, and J. Zerbe. CICC, page 1-4. IEEE, (2012)A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS.K. Kaviani, M. Hossain, M. Nazari, F. Heaton, J. Ren, and J. Zerbe. CICC, page 1-4. IEEE, (2012)Equalizer design and performance trade-offs in ADC-based serial links.J. Kim, J. Ren, B. Leibowitz, P. Satarzadeh, A. Abbasfar, and J. Zerbe. CICC, page 1-8. IEEE, (2010)Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links.J. Kim, E. Chen, J. Ren, B. Leibowitz, P. Satarzadeh, J. Zerbe, and C. Yang. IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (9): 2096-2107 (2011)A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology.R. Navid, E. Chen, M. Hossain, B. Leibowitz, J. Ren, C. Chou, B. Daly, M. Aleksic, B. Su, S. Li and 4 other author(s). IEEE J. Solid State Circuits, 50 (4): 814-827 (2015)A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface.H. Lee, K. Chang, J. Chun, T. Wu, Y. Frans, B. Leibowitz, N. Nguyen, T. Chin, K. Kaviani, J. Shen and 10 other author(s). IEEE J. Solid State Circuits, 44 (4): 1235-1247 (2009)Transition-limiting codes for 4-PAM signaling in high speed serial links.A. Bessios, W. Stonecypher, A. Agarwal, and J. Zerbe. GLOBECOM, page 3747-3751. IEEE, (2003)

BibSonomy

Disambiguation of "Zerbe, Jared"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching.

Please choose a person to relate this publication to

Jared Sonnicksen

Jared Wicks

Jared Miller

Jared Dulmage

Jared Leo

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Zerbe, Jared"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching.

Please choose a person to relate this publication to

Jared Sonnicksen

Jared Wicks

Jared Miller

Jared Dulmage

Jared Leo

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching.