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Disambiguation of "Kawaguchi, Hiroshi"

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Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path.

, , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 99-A (6): 1198-1205 (2016)

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Hirokazu Kawaguchi

Hiroshi Kawabe

Hiroshi Murata

Hiroshi Kubota

Hiroshi Uchida

 

Other publications of authors with the same name

A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current., , and . IEEE J. Solid State Circuits, 35 (10): 1498-1501 (2000)A Case Study for Improving Performances of Deep-Learning Processor with MRAM., , , , , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2024)A 1.15-TOPS 6.57-TOPS/W Neural Network Processor for Multi-Scale Object Detection With Reduced Convolutional Operations., , , , , , , , , and . IEEE J. Sel. Top. Signal Process., 14 (4): 634-645 (2020)Signal contributions to heavily diffusion-weighted functional magnetic resonance imaging investigated with multi-SE-EPI acquisitions., , , , , , , and . NeuroImage, (2014)A Wearable Healthcare System With a 13.7 µ A Noise Tolerant ECG Processor., , , , , , , , , and 1 other author(s). IEEE Trans. Biomed. Circuits Syst., 9 (5): 733-742 (2015)Aggregation Efficiency-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks., , , , , and . IEICE Trans. Commun., 89-B (10): 2741-2751 (2006)A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture., , , , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (12): 3623-3633 (2006)A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 95-A (12): 2226-2233 (2012)Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's., , , , , , , , , and . IEICE Trans. Electron., 88-C (4): 760-767 (2005)A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond., , , , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (12): 3634-3641 (2006)