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A Compressed Breadth-First Search for Satisfiability., and . ALENEX, volume 2409 of Lecture Notes in Computer Science, page 29-42. Springer, (2002)Faster Schrödinger-style simulation of quantum circuits., and . CoRR, (2020)Optimal partitioners and end-case placers for standard-cell layout., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (11): 1304-1313 (2000)On wirelength estimations for row-based placement., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (9): 1265-1278 (1999)Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (12): 2107-2119 (2008)Synthesis of reversible logic circuits., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (6): 710-722 (2003)Resolution cannot polynomially simulate compressed-BFS., , and . Ann. Math. Artif. Intell., 44 (1-2): 121-156 (2005)Efficient Symmetry Breaking for Boolean Satisfiability., , and . IEEE Trans. Computers, 55 (5): 549-558 (2006)Capo: Congestion-Driven Placement for Standard-cell and RTL Netlists with Incremental Capability., , and . Modern Circuit Placement, Springer, (2007)Large-scale Boolean matching., and . DATE, page 771-776. IEEE Computer Society, (2010)