( en | de | ru )

 

Disambiguation of "Hayes, John P."

Author of the publication

copydeleteadd this publication to your clipboard
Synthesis of reversible logic circuits.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (6): 710-722 (2003)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Matthew John Hayes

John P Burrows

John P Brown

John P Broussard

John P Teschke

 

Other publications of authors with the same name

Tracking Uncertainty with Probabilistic Logic Circuit Testing., , and . IEEE Des. Test Comput., 24 (4): 312-321 (2007)Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering., , and . IEEE Des. Test Comput., 16 (3): 72-80 (1999)Online BIST for Embedded Systems., , and . IEEE Des. Test Comput., 15 (4): 17-24 (1998)Guest Editor's Introduction: Testing and Improving the Testability of Multimegabit Memories., and . IEEE Des. Test Comput., 10 (1): 6-7 (1993)Optimal Testing and Design of Adders., and . VLSI Design, 1 (4): 285-298 (1994)Zero-aliasing space compaction of test responses using multiple parity signatures., and . IEEE Trans. Very Large Scale Integr. Syst., 6 (2): 309-313 (1998)Optimal synthesis of linear reversible circuits., , and . Quantum Inf. Comput., 8 (3): 282-294 (2008)Scalable Test Generators for High-Speed Datapath Circuits., , and . J. Electron. Test., 12 (1-2): 111-125 (1998)A Fully Integrated Auto-Calibrated Super-Regenerative Receiver in 0.13-µm CMOS., , and . IEEE J. Solid State Circuits, 42 (9): 1976-1985 (2007)Realization-independent ATPG for designs with unimplemented blocks., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (2): 290-306 (2001)