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Disambiguation of "Chuang, Ching-Te"

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Design and CAD Challenges in sub-90nm CMOS Technologies.

, , , and . ICCAD, page 129-137. IEEE Computer Society / ACM, (2003)

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Shih-Te Chuang

Ching-yao Chuang

Ching-Ho Chuang

Wilhelm Ching

Paisal Chingduang

 

Other publications of authors with the same name

"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session)., , , and . ISLPED, page 203-206. ACM, (2000)Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell., , , , and . ISLPED, page 255-258. ACM, (2014)Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells., , , and . ISCAS, page 601-604. IEEE, (2015)Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness., , , , , and . ISCAS, page 2325-2328. IEEE, (2015)A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance., , , , , , and . ESSDERC, page 157-160. IEEE, (2012)Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications., , , , , , , , , and . BioCAS, page 238-241. IEEE, (2013)An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer., , , , , , , , , and 7 other author(s). ISCAS, page 1-4. IEEE, (2017)Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices., , , , , , and . Microelectron. J., 38 (8-9): 931-941 (2007)Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor., , , , , , , , , and 1 other author(s). IBM J. Res. Dev., 41 (4&5): 489-504 (1997)Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI., , , and . ISQED, page 145-152. IEEE Computer Society, (2007)