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Understanding Selective Delay as a Method for Efficient Secure Speculative Execution.

, , , , and . IEEE Trans. Computers, 69 (11): 1584-1595 (2020)

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Wrong-Path-Aware Entangling Instruction Prefetcher., and . IEEE Trans. Computers, 73 (2): 548-559 (February 2024)Speculative inter-thread store-to-load forwarding in SMT architectures., , , and . J. Parallel Distributed Comput., (March 2023)Compiler-Assisted Compaction/Restoration of SIMD Instructions., , , , , , and . IEEE Trans. Parallel Distributed Syst., 33 (4): 779-791 (2022)Analysing software prefetching opportunities in hardware transactional memory., , , , , , and . J. Supercomput., 78 (1): 919-944 (2022)Exploring Instruction Fusion Opportunities in General Purpose Processors., , , and . MICRO, page 199-212. IEEE, (2022)Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs., , and . Euro-Par Workshops (2), volume 8806 of Lecture Notes in Computer Science, page 254-265. Springer, (2014)Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks., , , , and . ISCA, page 93-104. ACM, (2011)Efficient invisible speculative execution through selective delay and value prediction., , , , and . ISCA, page 723-735. ACM, (2019)A new perspective for efficient virtual-cache coherence., and . ISCA, page 535-546. ACM, (2013)Non-Speculative Store Coalescing in Total Store Order., and . ISCA, page 221-234. IEEE Computer Society, (2018)