( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Understanding Selective Delay as a Method for Efficient Secure Speculative Execution.

, , , , и . IEEE Trans. Computers, 69 (11): 1584-1595 (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Arno Ros

Guido Ros

Margarete Ros

Gisela Ros

Gisela Ros

 

Другие публикации лиц с тем же именем

To be silent or not: on the impact of evictions of clean data in cache-coherent multicores., , и . J. Supercomput., 73 (10): 4428-4443 (2017)PS-Cache: an energy-efficient cache design for chip multiprocessors., , , и . J. Supercomput., 71 (1): 67-86 (2015)Extending Magny-Cours Cache Coherence., , , , , , , и . IEEE Trans. Computers, 61 (5): 593-606 (2012)Fine-grain data classification to filter token coherence traffic., , и . J. Parallel Distributed Comput., (января 2023)PfTouch: Concurrent page-fault handling for Intel restricted transactional memory., , , и . J. Parallel Distributed Comput., (2020)Photonic-based express coherence notifications for many-core CMPs., , , и . J. Parallel Distributed Comput., (2018)Understanding Selective Delay as a Method for Efficient Secure Speculative Execution., , , , и . IEEE Trans. Computers, 69 (11): 1584-1595 (2020)Way Combination for an Adaptive and Scalable Coherence Directory., , , , , , и . IEEE Trans. Parallel Distributed Syst., 30 (11): 2608-2623 (2019)TokenTLB+CUP: A Token-Based Page Classification with Cooperative Usage Prediction., , , и . IEEE Trans. Parallel Distributed Syst., 29 (5): 1188-1201 (2018)Concurrent Irrevocability in Best-Effort Hardware Transactional Memory., , , и . IEEE Trans. Parallel Distributed Syst., 31 (6): 1301-1315 (2020)