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Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs.

, , , и . VLSI Design, стр. 329-334. IEEE Computer Society, (2003)

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Cascade Realization of 3-Input 3-Output Conservative Logic Circuits., и . IEEE Trans. Computers, 27 (3): 214-221 (1978)Design of High-Level Test Language for Digital LSI., , и . ITC, стр. 508-513. IEEE Computer Society, (1983)Removal of Redundancy in Logic Circuits under Classification of Undetectable Faults., , и . FTCS, стр. 263-270. IEEE Computer Society, (1992)A Novel ATPG Method for Capture Power Reduction during Scan Testing., , , , , , и . IEICE Trans. Inf. Syst., 90-D (9): 1398-1405 (2007)Design of testing circuit and test generation for built-in current testing., , и . Syst. Comput. Jpn., 24 (5): 73-82 (1993)An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits., , и . Asian Test Symposium, стр. 22-. IEEE Computer Society, (1997)IDDQ Current Dependency on Test Vectors and Bridging Resistance., , и . Asian Test Symposium, стр. 158-163. IEEE Computer Society, (1999)Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique., , и . Asian Test Symposium, стр. 94-99. IEEE Computer Society, (1996)Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits., , и . Asian Test Symposium, стр. 121-126. IEEE Computer Society, (1999)Low-capture-power test generation for scan-based at-speed testing., , , , , , и . ITC, стр. 10. IEEE Computer Society, (2005)