Author of the publication

Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories.

, , and . MTDT, page 119-124. IEEE Computer Society, (2000)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Design and Test of a 9-port SRAM for a 100Gb/s STS-1 Switch., , , , and . MTDT, page 83-. IEEE Computer Society, (2002)Quad DCVS dynamic logic fault modeling and testing., , and . ITC, page 356-362. IEEE Computer Society, (1998)The Limits of Digital Testing for Dynamic Circuits., and . VTS, page 28-33. IEEE Computer Society, (1999)A Self-Test Circuit for Evaluating Memory Sense-Amplifier Signal., , and . ITC, page 217-225. IEEE Computer Society, (1997)Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories., , and . MTDT, page 119-124. IEEE Computer Society, (2000)Deterministic Self-Test of a High-Speed Embedded Memory and Logic Processor Subsystem., , , and . ITC, page 33-44. IEEE Computer Society, (1995)Bitline contacts in high density SRAMs: design for testability and stressability., , , , and . ITC, page 776-782. IEEE Computer Society, (2001)Defect Analysis and a New Fault Model for Multi-port SRAMs., , , and . DFT, page 366-374. IEEE Computer Society, (2001)A 370-MHz memory built-in self-test state machine., , , and . ED&TC, page 139-143. IEEE Computer Society, (1995)Self test architecture for testing complex memory structures., , , and . ITC, page 547-556. IEEE Computer Society, (2000)