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CTLE-Ising:A 1440-Spin Continuous-Time Latch-Based isling Machine with One-Shot Fully-Parallel Spin Updates Featuring Equalization of Spin States.

, , , and . ISSCC, page 142-143. IEEE, (2023)

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A Reconfigurable lsing Machine for Boolean Satisfiability Problems Featuring Many-Body Spin Interactions., , and . CICC, page 1-2. IEEE, (2023)A 32x32 Time-Domain Wavefront Computing Accelerator for Path Planning and Scientific Simulations., , , , and . CICC, page 1-2. IEEE, (2021)A 0.2-1.45-GHz Subsampling Fractional-N Digital MDLL With Zero-Offset Aperture PD-Based Spur Cancellation and In Situ Static Phase Offset Detection., , and . IEEE J. Solid State Circuits, 52 (3): 799-811 (2017)A 28Gb/s transceiver with chirp-managed EDC for DML systems., , , , , , , , , and 1 other author(s). ISSCC, page 264-266. IEEE, (2018)A Scalable and Reconfigurable Bit-Serial Compute-Near-Memory Hardware Accelerator for Solving 2-D/3-D Partial Differential Equations., , , and . IEEE J. Solid State Circuits, 59 (8): 2706-2716 (August 2024)A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit., , and . VLSIC, page 140-. IEEE, (2015)19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection., , and . ISSCC, page 326-327. IEEE, (2016)A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer., , , , , , , , and . CICC, page 237-240. IEEE, (2008)Low-Complexity Tree Architecture for Finding the First Two Minima., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (1): 61-64 (2015)A Scalable Bit-Serial Computing Hardware Accelerator for Solving 2D/3D Partial Differential Equations Using Finite Difference Method., , , and . ESSCIRC, page 353-356. IEEE, (2022)