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Blocked United Algorithm for the All-Pairs Shortest Paths Problem on Hybrid CPU-GPU Systems.

, , and . IEICE Trans. Inf. Syst., 95-D (12): 2759-2768 (2012)

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Blocked United Algorithm for the All-Pairs Shortest Paths Problem on Hybrid CPU-GPU Systems., , and . IEICE Trans. Inf. Syst., 95-D (12): 2759-2768 (2012)Orbital Systolic Algorithms and Array Processors for Solution of the Algebraic Path Problem., , and . IEICE Trans. Inf. Syst., 93-D (3): 534-541 (2010)3D-DCT Processor and Its FPGA Implementation., , and . IEICE Trans. Inf. Syst., 94-D (7): 1409-1418 (2011)An Algorithm and Array Processor for Solving the Systems of Linear Equations.. PDPTA, page 307-316. CSREA Press, (1995)Implementing a Code Generator for Fast Matrix Multiplication in OpenCL on the GPU., , and . MCSoC, page 198-204. IEEE Computer Society, (2012)Blocked All-Pairs Shortest Paths Algorithm for Hybrid CPU-GPU System., , and . HPCC, page 145-152. IEEE, (2011)Computationally Efficient Parallel Matrix-Matrix Multiplication on the Torus., and . ISHPC, volume 4759 of Lecture Notes in Computer Science, page 219-226. Springer, (2005)Matrix Transpose on 2D Torus Array Processor., and . CIT, page 45. IEEE Computer Society, (2006)2-D Separable Transforms on a Matrix Processor., and . CAINE, page 106-111. ISCA, (2008)Parallelism for High-Performance Tsunami Simulation with FPGA: Spatial or Temporal?, , , , , and . FCCM, page 30. IEEE Computer Society, (2016)