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Disambiguation of "Sakiyama, Shiro"

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A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques.

, , , , , , , and . IEEE J. Solid State Circuits, 50 (6): 1372-1381 (2015)

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Shiro Kobayashi

Shiro Takebayashi

Shiro Kobayashi

Shiro Yukawa

Shiro Ando

 

Other publications of authors with the same name

A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques., , , , , , , and . IEEE J. Solid State Circuits, 50 (6): 1372-1381 (2015)Mixed body bias techniques with fixed Vt and Ids generation circuits., , , , , and . IEEE J. Solid State Circuits, 40 (1): 60-66 (2005)An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage., , , and . ISSCC, page 404-405. IEEE, (2009)A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise., , , , , , , and . ISSCC, page 272-273. IEEE, (2013)A Low Distortion 3rd-Order Continuous-Time Delta-Sigma Modulator for a Worldwide Digital TV-Receiver., , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 95-A (2): 471-478 (2012)A 0.03mm2 9mW Wide-Range Duty-Cycle Correcting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface., , , , and . ISSCC, page 1286-1295. IEEE, (2006)Quantizer neuron model and neuroprocessor-named quantizer neuron chip., , , , and . IEEE J. Sel. Areas Commun., 12 (9): 1503-1509 (1994)A 69.8 dB SNDR 3rd-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver., , , , , , and . CICC, page 1-4. IEEE, (2010)Design methods for pipeline & delta-sigma A-to-D converters with convex optimization., , , , , , , , , and . ASP-DAC, page 690-695. IEEE, (2009)A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution., , , , and . ISSCC, page 2422-2431. IEEE, (2006)