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Disambiguation of "Dosho, Shiro"

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A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques.

, , , , , , , and . IEEE J. Solid State Circuits, 50 (6): 1372-1381 (2015)

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Shiro Kobayashi

Shiro Takebayashi

Shiro Kobayashi

Shiro Yukawa

Shiro Ando

 

Other publications of authors with the same name

A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise., , , , , , , and . ISSCC, page 272-273. IEEE, (2013)An Ultra-Wide Range Bi-Directional Transceiver With Adaptive Power Control Using Background Replica VCO Gain Calibration., , , , , , and . IEEE J. Solid State Circuits, 46 (4): 986-991 (2011)An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects., , , and . IEEE J. Solid State Circuits, 47 (11): 2773-2782 (2012)A -90 dBc@ 10 kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit., , , , and . IEICE Trans. Electron., 89-C (6): 739-745 (2006)A Low Distortion 3rd-Order Continuous-Time Delta-Sigma Modulator for a Worldwide Digital TV-Receiver., , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 95-A (2): 471-478 (2012)A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS., , , , and . IEICE Trans. Electron., 100-C (6): 560-567 (2017)A 0.03mm2 9mW Wide-Range Duty-Cycle Correcting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface., , , , and . ISSCC, page 1286-1295. IEEE, (2006)A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-μm CMOS process., , and . IEEE J. Solid State Circuits, 37 (5): 559-565 (2002)A 69.8 dB SNDR 3rd-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver., , , , , , and . CICC, page 1-4. IEEE, (2010)Design methods for pipeline & delta-sigma A-to-D converters with convex optimization., , , , , , , , , and . ASP-DAC, page 690-695. IEEE, (2009)