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Disambiguation of "Krishnamurthy, Ram K."

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Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference.

, , , and . IEEE J. Solid State Circuits, 44 (1): 3-6 (2009)

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Mahalakshmi Krishnamurthy

Adarsh Krishnamurthy

Arvind Krishnamurthy

Ram Gopal

Johann Ram

 

Other publications of authors with the same name

Exploring the design space of mixed swing quadrail for low-power digital circuits., and . IEEE Trans. Very Large Scale Integr. Syst., 5 (4): 388-400 (1997)Energy efficient and ultra low voltage security circuits for nanoscale CMOS technologies., , , and . CICC, page 1-4. IEEE, (2017)A leakage-tolerant low-leakage register file with conditional sleep transistor., , and . SoCC, page 241-244. IEEE, (2004)A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS., , , , , and . IEEE J. Solid State Circuits, 40 (1): 44-51 (2005)A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 55 (4): 945-955 (2020)A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS., , , , , , , , , and 1 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)A 200mV to 1.2V, 4.4MHz to 6.3GHz, 48×42b 1R/1W programmable register file in 65nm CMOS., , , , and . ESSCIRC, page 316-319. IEEE, (2007)microASR: 32-μW Real-Time Automatic Speech Recognition Chip featuring a Bio-Inspired Neuron Model and Digital SRAM-based Compute-In-Memory Hardware., , , , , and . ESSCIRC, page 421-424. IEEE, (2023)16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS., , , , , , , , , and . ISSCC, page 276-277. IEEE, (2014)High-performance and low-power challenges for sub-70 nm microprocessor circuits., , , and . CICC, page 125-128. IEEE, (2002)