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110GHz Through-Silicon Via's Integrated in Silicon Photonics Interposers for Next-Generation Optical Modules.

, , , , , , , , , and . ECOC, page 1-4. IEEE, (2021)

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Modeling FinFET metal gate stack resistance for 14nm node and beyond., , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes., , , , , , , , , and 5 other author(s). Microprocess. Microsystems, 39 (8): 1039-1051 (2015)On the ballistic ratio in 14nm-Node FinFETs., , , , and . ESSDERC, page 176-179. IEEE, (2017)STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process., , , , , , , , and . ESSDERC, page 159-162. IEEE, (2013)Impact of fin shape variability on device performance towards 10nm node., , , , , , , , , and 3 other author(s). ICICDT, page 1-4. IEEE, (2015)Device Scaling roadmap and its implications for Logic and Analog platform., , , , , , and . BCICTS, page 1-8. IEEE, (2020)Design Technology co-optimization for N10., , , , , , , , , and 18 other author(s). CICC, page 1-8. IEEE, (2014)Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node., , , , , , , , , and 7 other author(s). VLSI Technology and Circuits, page 429-430. IEEE, (2022)110GHz Through-Silicon Via's Integrated in Silicon Photonics Interposers for Next-Generation Optical Modules., , , , , , , , , and . ECOC, page 1-4. IEEE, (2021)