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Disambiguation of "Horiguchi, N."

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On the ballistic ratio in 14nm-Node FinFETs.

, , , , and . ESSDERC, page 176-179. IEEE, (2017)

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Tomonaga Horiguchi

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N -L N Nguyen

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Other publications of authors with the same name

Novel Low Thermal Budget CMOS RMG: Performance and Reliability Benchmark Against Conventional High Thermal Budget Gate Stack Solutions., , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets., , , , , , , , , and 1 other author(s). IRPS, page 5. IEEE, (2022)Novel low thermal budget gate stack solutions for BTI reliability in future Logic Device technologies : Invited paper., , , , , , , , , and 3 other author(s). ICICDT, page 1-4. IEEE, (2021)Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks., , , , , , , , , and 2 other author(s). ESSDERC, page 242-245. IEEE, (2012)Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements., , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (7): 439-442 (2012)Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning., , , , , , , , , and 30 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Molybdenum Nitride as a Scalable and Thermally Stable pWFM for CFET., , , , , , , , , and 11 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling., , , , , , , and . ICICDT, page 51-54. IEEE, (2022)Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery., , , , , , , , , and 7 other author(s). IRPS, page 1-6. IEEE, (2022)Experimental evidences and simulations of trap generation along a percolation path., , , , , , , , , and . ESSDERC, page 226-229. IEEE, (2015)