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F3: Emerging technologies for wireline communication., , , , , , and . ISSCC, page 504-505. IEEE, (2013)Session 23 overview: Short-reach links, XCVR techniques, & PLLs., and . ISSCC, page 398-399. IEEE, (2013)Current-steering pre-emphasis transmitter with continuously tuned line terminations for optimum impedance match and maximum signal drive range., , and . CICC, page 1-4. IEEE, (2013)High-speed wireline transceivers and clocking., and . CICC, page 1-2. IEEE, (2012)Applying Asynchronous Circuits in Contactless Smart Cards., , , , and . ASYNC, page 36-44. IEEE Computer Society, (2000)A 1.2-6 Gb/s, 4.2 pJ/bit Clock & Data Recovery circuit with high jitter tolerance in 0.14μm CMOS., and . ESSCIRC, page 167-170. IEEE, (2011)A 1.2-6 Gb/s, 4.2 pJ/Bit Clock & Data Recovery Circuit With High Jitter Tolerance in 0.14 µm CMOS., and . IEEE J. Solid State Circuits, 47 (7): 1768-1775 (2012)Session 10 overview: Advanced wireline techniques and PLLs: Wireline subcommittee., and . ISSCC, page 174-175. IEEE, (2015)F4: Emerging short-reach and high-density interconnect solutions for internet of everything., , , , , and . ISSCC, page 502-505. IEEE, (2016)Single-Pair Automotive PHY Solutions from 10Mb/s to 10Gb/s and Beyond.. ISSCC, page 474-476. IEEE, (2019)