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pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction.

T. Oh, Y. Sohn, S. Bae, M. Park, J. Lim, Y. Cho, D. Kim, D. Kim, H. Kim, H. Kim, J. Kim, J. Kim, Y. Kim, B. Kim, S. Kwak, J. Lee, J. Lee, C. Shin, Y. Yang, B. Cho, S. Bang, H. Yang, Y. Choi, G. Moon, C. Park, S. Hwang, J. Lim, K. Park, J. Choi, and Y. Jun. ISSCC, page 434-435. IEEE, (2010)

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Jun-Sang Bae

Jung-Hun Seung

Soonil Bae

Jun Jun Lu

Han Bae

Other publications of authors with the same name

18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution.H. Joo, S. Bae, Y. Sohn, Y. Kim, K. Ha, M. Ahn, Y. Kim, Y. Kim, J. Kim, W. Choi and 7 other author(s). ISSCC, page 314-315. IEEE, (2016)An on-chip TSV emulation using metal bar surrounded by metal ring to develop interface circuits.I. Yi, S. Bae, Y. Sohn, J. Sim, and H. Park. ISOCC, page 192-195. IEEE, (2012)A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel.J. Bae, Y. Sohn, S. Bae, K. Park, J. Choi, Y. Jun, J. Sim, and H. Park. CICC, page 1-4. IEEE, (2010)A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling.S. Bae, H. Chi, Y. Sohn, J. Lee, J. Sim, and H. Park. IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (8): 1645-1656 (2009)A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process.J. Baek, C. Lee, K. Kim, D. Moon, G. Cha, J. Heo, M. Ahn, D. Kim, J. Song, S. Kwon and 16 other author(s). VLSI Circuits, page 147-148. IEEE, (2018)A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.Y. Kim, H. Kwon, S. Doo, M. Ahn, Y. Kim, Y. Lee, D. Kang, S. Do, C. Lee, G. hee Cho and 29 other author(s). IEEE J. Solid State Circuits, 54 (1): 197-209 (2019)Introduction to the Special Issue on the 2018 International Solid-State Circuits Conference (ISSCC).Y. Frans, W. Dehaene, M. Motomura, and S. Bae. IEEE J. Solid State Circuits, 54 (1): 3-5 (2019)A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques.K. Ha, S. Lee, Y. Park, H. Kwon, T. Oh, Y. Sohn, S. Bae, K. Park, J. Lee, C. Lee and 7 other author(s). IEEE J. Solid State Circuits, 55 (1): 157-166 (2020)A Duo-Binary Transceiver With Time-Based Receiver and Voltage-Mode Time-Interleaved Mixing Transmitter for DRAM Interface.M. Chae, H. Kwon, S. Bae, N. Kim, and H. Park. IEEE Trans. Circuits Syst. II Express Briefs, 68 (7): 2409-2413 (2021)A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination.I. Yi, S. Lee, S. Bae, Y. Sohn, J. Choi, B. Kim, J. Sim, and H. Park. IEEE Trans. Circuits Syst. II Express Briefs, 61-II (12): 987-991 (2014)

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Disambiguation of "Bae, Seung-Jun"

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A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction.

Please choose a person to relate this publication to

Jun-Sang Bae

Jung-Hun Seung

Soonil Bae

Jun Jun Lu

Han Bae

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Bae, Seung-Jun"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction.

Please choose a person to relate this publication to

Jun-Sang Bae

Jung-Hun Seung

Soonil Bae

Jun Jun Lu

Han Bae

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction.