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pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction.

T. Oh, Y. Sohn, S. Bae, M. Park, J. Lim, Y. Cho, D. Kim, D. Kim, H. Kim, H. Kim, J. Kim, J. Kim, Y. Kim, B. Kim, S. Kwak, J. Lee, J. Lee, C. Shin, Y. Yang, B. Cho, S. Bang, H. Yang, Y. Choi, G. Moon, C. Park, S. Hwang, J. Lim, K. Park, J. Choi, and Y. Jun. ISSCC, page 434-435. IEEE, (2010)

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Young-Soo Chang

Soo-Young Kim

Young-Soo Han

Young-Taek Sohn

Hae-Young Sohn

Other publications of authors with the same name

A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme.J. Sim, J. Nam, Y. Sohn, H. Park, C. Kim, and S. Cho. IEEE J. Solid State Circuits, 37 (2): 245-250 (2002)An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface.Y. Kim, S. Lee, S. Bae, Y. Sohn, J. Lee, J. Choi, H. Park, and J. Sim. ISSCC, page 136-138. IEEE, (2012)Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond.J. Kim, S. Kang, S. Lee, H. Kim, W. Song, Y. Ro, S. Lee, D. Wang, H. Shin, B. Phuah and 10 other author(s). HCS, page 1-26. IEEE, (2021)18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution.H. Joo, S. Bae, Y. Sohn, Y. Kim, K. Ha, M. Ahn, Y. Kim, Y. Kim, J. Kim, W. Choi and 7 other author(s). ISSCC, page 314-315. IEEE, (2016)An on-chip TSV emulation using metal bar surrounded by metal ring to develop interface circuits.I. Yi, S. Bae, Y. Sohn, J. Sim, and H. Park. ISOCC, page 192-195. IEEE, (2012)A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel.J. Bae, Y. Sohn, S. Bae, K. Park, J. Choi, Y. Jun, J. Sim, and H. Park. CICC, page 1-4. IEEE, (2010)A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling.S. Bae, H. Chi, Y. Sohn, J. Lee, J. Sim, and H. Park. IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (8): 1645-1656 (2009)An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM.J. Moon, H. Yoo, H. Choi, I. Park, S. Kang, J. Kim, H. Chung, K. Kim, D. Lee, K. Song and 7 other author(s). A-SSCC, page 139-142. IEEE, (2018)A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process.J. Baek, C. Lee, K. Kim, D. Moon, G. Cha, J. Heo, M. Ahn, D. Kim, J. Song, S. Kwon and 16 other author(s). VLSI Circuits, page 147-148. IEEE, (2018)A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.Y. Kim, H. Kwon, S. Doo, M. Ahn, Y. Kim, Y. Lee, D. Kang, S. Do, C. Lee, G. hee Cho and 29 other author(s). IEEE J. Solid State Circuits, 54 (1): 197-209 (2019)

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Disambiguation of "Sohn, Young-Soo"

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A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction.

Please choose a person to relate this publication to

Young-Soo Chang

Soo-Young Kim

Young-Soo Han

Young-Taek Sohn

Hae-Young Sohn

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Sohn, Young-Soo"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction.

Please choose a person to relate this publication to

Young-Soo Chang

Soo-Young Kim

Young-Soo Han

Young-Taek Sohn

Hae-Young Sohn

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction.