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A Sub-THz Full-Duplex Phased-Array Transceiver with Self-Interference Cancellation and LO Feedthrough Suppression.

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A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 59 (4): 978-992 (April 2024)A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 57 (6): 1723-1735 (2022)A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter., , , , , , , , , and 4 other author(s). ISSCC, page 445-447. IEEE, (2021)32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays., , , , , , , , , and 5 other author(s). ISSCC, page 456-458. IEEE, (2021)A Sub-THz Full-Duplex Phased-Array Transceiver with Self-Interference Cancellation and LO Feedthrough Suppression., , , , , , , , , and 5 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)24.3 A 236-to-266GHz 4-Element Amplifier-Last Phased-Array Transmitter in 65nm CMOS., , , , , , , , , and 9 other author(s). ISSCC, page 415-417. IEEE, (2024)