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Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (4): 1497-1505 (2017)

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Test reordering for improved scan chain diagnosis using an enhanced defect diagnosis procedure., , , and . ITC, page 1-9. IEEE, (2017)Fault equivalence identification in combinational circuits using implication and evaluation techniques., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (7): 922-936 (2003)Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction., , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (4): 1497-1505 (2017)Defect diagnosis based on DFM guidelines., , , and . VTS, page 206-211. IEEE Computer Society, (2010)Test Modification for Reduced Volumes of Fail Data., , and . ACM Trans. Design Autom. Electr. Syst., 22 (4): 67:1-67:17 (2017)An Experimental Study of N-Detect Scan ATPG Patterns on a Processor., , , , , and . VTS, page 23-30. IEEE Computer Society, (2004)Innovative practices session 5C: Advancements in test -keeping moore moving!. VTS, page 1. IEEE Computer Society, (2015)Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits., , and . VTS, page 181-186. IEEE Computer Society, (2002)Using Scan-Dump Values to Improve Functional-Diagnosis Methodology., , , , , and . VTS, page 231-238. IEEE Computer Society, (2007)A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction., , and . ATS, page 138-143. IEEE Computer Society, (2016)