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Disambiguation of "Castrillón, Jerónimo"

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Application-aware spinlock control using a hardware scheduler in MPSoC platforms.

, , , , , , and . ISSoC, page 1-6. IEEE, (2012)

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Jeronimo Castrillon Mazo

Jerónimo Rodríguez

Jerónimo José Granados

Antonio Castrillón H

Elkin Castrillón Oberndorfer

 

Other publications of authors with the same name

Achieving Determinism in Adaptive AUTOSAR., , , and . DATE, page 822-827. IEEE, (2020)Generalized Data Placement Strategies for Racetrack Memories., , , and . DATE, page 1502-1507. IEEE, (2020)RTSim: A Cycle-Accurate Simulator for Racetrack Memories., , , , and . IEEE Comput. Archit. Lett., 18 (1): 43-46 (2019)Pruning and Early-Exit Co-Optimization for CNN Acceleration on FPGAs., , , , and . DATE, page 1-6. IEEE, (2023)DownShift: Tuning Shift Reduction With Reliability for Racetrack Memories., , , , and . IEEE Trans. Computers, 72 (9): 2585-2599 (September 2023)Optimized communication architecture of MPSoCs with a hardware scheduler: A system view., , , , , , and . SoC, page 163-168. IEEE, (2010)Reactors: A Deterministic Model for Composable Reactive Systems., , , , , , and . CyPhy/WESE, volume 11971 of Lecture Notes in Computer Science, page 59-85. Springer, (2019)Application-aware spinlock control using a hardware scheduler in MPSoC platforms., , , , , , and . ISSoC, page 1-6. IEEE, (2012)Efficient Memory Layout for Pre-Alignment Filtering of Long DNA Reads Using Racetrack Memory., , , , and . IEEE Comput. Archit. Lett., 23 (1): 129-132 (January 2024)Guard the Cache: Dispatch Optimization in a Contextual Role-oriented Language., , and . COP@ECOOP, page 27-34. ACM, (2022)