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Ultra-Low Power Hybrid CMOS-Magnetic Logic Architecture.

, , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (9): 2008-2016 (2012)

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Auxiliary Roles in STT-MRAM Memory.. University of South Florida, Tampa, USA, (2014)base-search.net (ftunisfloridatam:oai:digitalcommons.usf.edu:etd-6818).Nano Magnetic STT-Logic Partitioning for Optimum Performance., , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (1): 90-98 (2014)MRAM PUF: Using Geometric and Resistive Variations in MRAM Cells., , and . JETC, 13 (1): 2:1-2:15 (2016)Ultra-Low Power Hybrid CMOS-Magnetic Logic Architecture., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (9): 2008-2016 (2012)Non-destructive variability tolerant differential read for non-volatile logic., , and . MWSCAS, page 178-181. IEEE, (2012)STT-Based Non-Volatile Logic-in-Memory Framework., , and . Field-Coupled Nanocomputing, volume 8280 of Lecture Notes in Computer Science, Springer, (2014)Low Power Magnetic Quantum Cellular Automata Realization Using Magnetic Multi-Layer Structures., , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (3): 267-276 (2011)Energy Barrier Model of SRAM for Improved Energy and Error Rates., and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (8): 2299-2308 (2014)Survey of Emerging Technology Based Physical Unclonable Funtions., , and . ACM Great Lakes Symposium on VLSI, page 317-322. ACM, (2016)