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Disambiguation of "Alam, Syed M."

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Ultra-Low Power Hybrid CMOS-Magnetic Logic Architecture.

, , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (9): 2008-2016 (2012)

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Masoom Alam

Renate Syed

Adnan Shahzad Syed

Homayun Alam

Fakhrul Alam

 

Other publications of authors with the same name

STT-Based Non-Volatile Logic-in-Memory Framework., , and . Field-Coupled Nanocomputing, volume 8280 of Lecture Notes in Computer Science, Springer, (2014)Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies., , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (4): 647-658 (2011)Design tool and methodologies for interconnect reliability analysis in integrated circuits.. Massachusetts Institute of Technology, Cambridge, MA, USA, (2004)ndltd.org (oai:dspace.mit.edu:1721.1/26722).Circuit Level Reliability Analysis of Cu Interconnects., , , and . ISQED, page 238-243. IEEE Computer Society, (2004)Low Power Magnetic Quantum Cellular Automata Realization Using Magnetic Multi-Layer Structures., , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (3): 267-276 (2011)Technology, CAD tools, and designs for emerging 3D integration technology., , and . ACM Great Lakes Symposium on VLSI, page 1-2. ACM, (2008)Reliability computer-aided design tool for full-chip electromigration analysis and comparison with different interconnect metallizations., , , and . Microelectron. J., 38 (4-5): 463-473 (2007)A 180 Kbit Embeddable MRAM Memory Module., , , , , , , and . IEEE J. Solid State Circuits, 43 (8): 1826-1834 (2008)A 180 Kbit Embeddable MRAM Memory Module., , , , , , and . CICC, page 791-794. IEEE, (2007)A Comprehensive Layout Methodology and Layout-Specific Circuit Analyses for Three-Dimensional Integrated Circuits., , and . ISQED, page 246-251. IEEE Computer Society, (2002)