( en | de | ru )

 

Disambiguation of "Tsukamoto, Yasumasa"

Author of the publication

copydeleteadd this publication to your clipboard
A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry.

, , , , , , and . ISQED, page 438-441. IEEE, (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Masaji Tsukamoto

Masaaki Tsukamoto

Nobuko Ohashi Tsukamoto

 

Other publications of authors with the same name

NBTI/PBTI separated BTI monitor with 4.2x sensitivity by standard cell based unbalanced ring oscillator., , , , and . A-SSCC, page 201-204. IEEE, (2017)A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 43 (1): 180-191 (2008)A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 43 (1): 96-108 (2008)A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure., , , , , and . CICC, page 1-4. IEEE, (2013)A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure., , , , , and . ISCAS (1), page 73-76. IEEE, (2005)A stable chip-ID generating physical uncloneable function using random address errors in SRAM., , , , , , and . SoCC, page 143-147. IEEE, (2012)Optimization of importance sampling Monte Carlo using consecutive mean-shift method and its application to SRAM dynamic stability analysis., , and . ISQED, page 572-579. IEEE, (2012)28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique., , , , , , , , , and 1 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 22 (3): 575-584 (2014)Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability., , , , , , , , and . ICCAD, page 398-405. IEEE Computer Society, (2005)A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS., , , , , , and . IEEE J. Solid State Circuits, 48 (4): 917-923 (2013)