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Disambiguation of "Zjajo, Amir"

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Transistor-level gate model based statistical timing analysis considering correlations.

, , , and . DATE, page 917-922. IEEE, (2012)

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Manutschehr Amirfeyz

Iradj Amirzadeh-Asl

Mahmud Amirian-Khaffadjeh

Belal Amireh

Mansoor Anwer Ismail Amir

 

Other publications of authors with the same name

Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (2): 210-223 (2014)A 0.1pJ Freeze Vernier time-to-digital converter in 65nm CMOS., , , and . ISCAS, page 85-88. IEEE, (2014)Integrated System-on-Module for Design-Space Exploration of Spiking Neural Networks., , , , , and . AICAS, page 1-5. IEEE, (2023)Physical characterization of steady-state temperature profiles in three-dimensional integrated circuits., , and . ISCAS, page 1969-1972. IEEE, (2015)A 11 µW 0°C-160°C temperature sensor in 90 nm CMOS for adaptive thermal monitoring of VLSI circuits., , and . ISCAS, page 2007-2010. IEEE, (2012)Digital spiking neuron cells for real-time reconfigurable learning networks., , and . SoCC, page 163-168. IEEE, (2017)Heterogeneous Activation Function Extraction for Training and Optimization of SNN Systems., , and . AICAS, page 244-245. IEEE, (2019)Statistical power optimization of deep-submicron digital CMOS circuits based on structured perceptron., , and . ISIC, page 95-98. IEEE, (2014)Energy-efficient neuromorphic receptors for wide-range temporal patterns of post-synaptic responses., , , and . NORCAS, page 1-6. IEEE, (2017)Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations., , , and . PATMOS, volume 6448 of Lecture Notes in Computer Science, page 190-199. Springer, (2010)