Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure.

S. Li, W. Zhao, B. Xu, X. Yang, X. Tang, L. Shen, N. Lu, D. Pan, and N. Sun. CICC, page 1-3. IEEE, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Yang Yang

Other publications of authors with the same name

A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM.J. Song, X. Tang, H. Luo, H. Zhang, X. Qiao, Z. Sun, X. Yang, Z. Wu, Y. Wang, R. Wang and 1 other author(s). IEEE J. Solid State Circuits, 59 (3): 842-854 (March 2024)A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC.J. Song, X. Tang, H. Luo, H. Zhang, X. Qiao, Z. Sun, X. Yang, Y. Wang, R. Wang, and R. Huang. CICC, page 1-2. IEEE, (2023)10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR.W. Shi, J. Liu, A. Mukherjee, X. Yang, X. Tang, L. Shen, W. Zhao, and N. Sun. ISSCC, page 170-172. IEEE, (2021)A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier.X. Tang, X. Yang, J. Liu, W. Shi, D. Pan, and N. Sun. ISSCC, page 376-378. IEEE, (2021)A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure.S. Li, W. Zhao, B. Xu, X. Yang, X. Tang, L. Shen, N. Lu, D. Pan, and N. Sun. CICC, page 1-3. IEEE, (2019)A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier.X. Tang, X. Yang, J. Liu, Z. Wang, W. Shi, D. Pan, and N. Sun. IEEE J. Solid State Circuits, 58 (9): 2564-2574 (September 2023)A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier.X. Tang, X. Yang, W. Zhao, C. Hsu, J. Liu, L. Shen, A. Mukherjee, W. Shi, S. Li, D. Pan and 1 other author(s). IEEE J. Solid State Circuits, 55 (12): 3248-3259 (2020)A Multi-Day Wearable Surface EMG E-Tattoo for Fatigue Monitoring.H. Huh, X. Yang, H. Shin, and N. Lu. EMBC, page 1-4. IEEE, (2023)A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter.X. Tang, S. Li, L. Shen, W. Zhao, X. Yang, R. Williams, J. Liu, Z. Tan, N. Hall, and N. Sun. ISSCC, page 296-297. IEEE, (2019)A 79dB-SNDR 167dB-FoM Bandpass ΔΣ ADC Combining N-Path Filter with Noise-Shaping SAR.L. Shen, Z. Gao, X. Yang, W. Shi, and N. Sun. ISSCC, page 382-384. IEEE, (2021)

BibSonomy

Disambiguation of "Yang, Xiangxing"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure.

Please choose a person to relate this publication to

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yang, Xiangxing"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure.

Please choose a person to relate this publication to

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure.