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Design and performance evaluation of a 2D-mesh Network on Chip prototype using FPGA., , , , , and . APCCAS, page 1264-1267. IEEE, (2008)A low power consumption, high speed Op-amp for a 10-bit 100MSPS parallel pipeline ADC., , , , and . APCCAS, page 818-821. IEEE, (2008)Design and implementation of homogeneous multi-core system., , , and . ASICON, page 788-791. IEEE, (2017)VLSI Architecture of Video Post-Processing System for MPEG/H.26X., , , , and . NCM, page 1520-1525. IEEE Computer Society, (2009)Study on the Multi-pipeline Reconfigurable Computing System., , and . CSSE (4), page 122-125. IEEE Computer Society, (2008)978-0-7695-3336-0.Performance analysis for matrix-multiplication based on an heterogeneous multi-core SoC., , , and . ASICON, page 1-4. IEEE, (2015)Scalability Study on Mesh Based Network on Chip., , , , , and . PACIIA (2), page 681-685. IEEE Computer Society, (2008)978-0-7695-3490-9.A technique of automatic monitor generation based on FSM., , , and . APCCAS, page 1775-1778. IEEE, (2008)A chain-multiplier for large scale matrix multiplication., , and . ASICON, page 792-795. IEEE, (2017)A low-latency DMM-1 encoder for 3D-HEVC., , , , , , and . J. Real Time Image Process., 17 (3): 691-702 (2020)