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An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors.

M. Fadiheh, A. Wezel, J. Müller, J. Bormann, S. Ray, J. Fung, S. Mitra, D. Stoffel, and W. Kunz. IEEE Trans. Computers, 72 (1): 222-235 (2023)

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Ian Jason

Siuwah Fung

Pat Fung

Reginald Fung

Michael Fung

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Secure-by-Construction Design Methodology for CPUs: Implementing Secure Speculation on the RTL.T. Jauch, A. Wezel, M. Fadiheh, P. Schmitz, S. Ray, J. Fung, C. Fletcher, D. Stoffel, and W. Kunz. ICCAD, page 1-9. IEEE, (2023)An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors.M. Fadiheh, A. Wezel, J. Müller, J. Bormann, S. Ray, J. Fung, S. Mitra, D. Stoffel, and W. Kunz. IEEE Trans. Computers, 72 (1): 222-235 (2023)Optimal Placement of TDC Sensor for Enhanced Power Side-Channel Assessment on FPGAS.D. Das, M. Sabbagh, R. Elnaggar, G. Chen, S. Ray, and J. Fung. VLSID, page 443-448. IEEE, (2024)Hardware-Supported Patching of Security Bugs in Hardware IP Blocks.W. Liu, B. Tan, J. Fung, R. Karri, and K. Chakrabarty. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (1): 54-67 (2023)Two Sides of the Same Coin: Boons and Banes of Machine Learning in Hardware Security.W. Liu, C. Chang, X. Wang, C. Liu, J. Fung, M. Ebrahimabadi, N. Karimi, X. Meng, and K. Basu. IEEE J. Emerg. Sel. Topics Circuits Syst., 11 (2): 228-251 (2021)Power Side-Channel Vulnerability Assessment of Lightweight Cryptographic Scheme, XOODYAK.A. Golder, D. Das, S. Ghosh, A. Varna, M. Sabbagh, S. Ray, R. Elnaggar, J. Friel, D. Dinu, and J. Fung. DAC, page 1-6. IEEE, (2023)Automating hardware security property generation: invited.R. Kastner, F. Restuccia, A. Meza, S. Ray, J. Fung, and C. Sturton. DAC, page 1384-1387. ACM, (2022)Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design.B. Ahmad, W. Liu, L. Collini, H. Pearce, J. Fung, J. Valamehr, M. Bidmeshki, P. Sapiecha, S. Brown, K. Chakrabarty and 2 other author(s). ICCAD, page 157:1-157:9. ACM, (2022)Theoretical Patchability Quantification for IP-Level Hardware Patching Designs.W. Liu, B. Tan, J. Fung, and K. Chakrabarty. ASPDAC, page 951-956. IEEE, (2024)Formal Verification of Security Critical Hardware-Firmware Interactions in Commercial SoCs.S. Ray, N. Ghosh, R. Masti, A. Kanuparthi, and J. Fung. DAC, page 43. ACM, (2019)

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Disambiguation of "Fung, Jason M."

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An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors.

Please choose a person to relate this publication to

Ian Jason

Siuwah Fung

Pat Fung

Reginald Fung

Michael Fung

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Fung, Jason M."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors.

Please choose a person to relate this publication to

Ian Jason

Siuwah Fung

Pat Fung

Reginald Fung

Michael Fung

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors.