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An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors.

, , , , , , , , and . IEEE Trans. Computers, 72 (1): 222-235 (2023)

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Normalization at the arithmetic bit level., , and . DAC, page 457-462. ACM, (2005)Arithmetic Constraints in SAT-based Property Checking., , , and . MBMV, page 91-100. Shaker, (2007)Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation., , , , , , , and . VLSI-SoC, page 1-6. IEEE, (2022)Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation., , , , and . MBMV, page 1-4. VDE/IEEE, (2022)MetaFS: Model-driven Fault Simulation Framework., , , , , , and . DFT, page 1-4. IEEE, (2022)Symbolic quick error detection using symbolic initial state for pre-silicon verification., , , , , , and . DATE, page 55-60. IEEE, (2018)Record & play: a structural fixed point iteration for sequential circuit verification., and . ICCAD, page 394-399. IEEE Computer Society / ACM, (1997)Data-Oblivious and Performant: On Designing Security-Conscious Hardware., , , , , , , and . LATS, page 1-6. IEEE, (2024)An Algebraic Approach for Proving Data Correctness in Arithmetic Data Paths., , , , and . CAV, volume 5123 of Lecture Notes in Computer Science, page 473-486. Springer, (2008)Towards the impact of state encoding on induction-based property checking., , and . MBMV, page 199-208. Shaker, (2003)