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A Dual-Input, Digital Hybrid Buck-LDO System Featuring Fast Load Transient Response, Zero-Wire Current Handover & Input PDN Resonance Reduction.

, , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2021)

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A Light-Load Efficient Fully Integrated Voltage Regulator in 14-nm CMOS With 2.5-nH Package-Embedded Air-Core Inductors., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 54 (12): 3316-3325 (2019)A Single-Chip Image Sensor Node With Energy Harvesting From a CMOS Pixel Array., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (9): 2295-2307 (2017)A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response., , , , , , , and . IEEE J. Solid State Circuits, 55 (4): 977-987 (2020)Reconfigurable 96×128 active pixel sensor with 2.1µW/mm2 power generation and regulated multi-domain power delivery for self-powered imaging., , , and . ESSCIRC, page 507-510. IEEE, (2016)A Dual-Input, Digital Hybrid Buck-LDO System Featuring Fast Load Transient Response, Zero-Wire Current Handover & Input PDN Resonance Reduction., , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2021)A single-inductor-cascaded-stage topology for high conversion ratio boost regulator., and . ICCD, page 487-491. IEEE Computer Society, (2016)Implementation of highly accurate NMOS Vt based clamping technique in low current comparator., , and . APCCAS, page 592-595. IEEE, (2010)28.4 A Monolithic 12.7W/mm2 Pmax, 92% Peak-Efficiency CSCR-First Switched-Capacitor DC-DC Converter., , , , , , , , , and . ISSCC, page 462-464. IEEE, (2024)Design of a linearly increasing inrush current limit circuit for DC-DC boost regulators., , , , and . APCCAS, page 863-866. IEEE, (2010)Peak-Current-Controlled Ganged Integrated High-Frequency Buck Voltage Regulators in 22nm CMOS for Robust Cross-Tile Current Sharing., , , , , , , , , and 1 other author(s). ISSCC, page 262-264. IEEE, (2021)