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Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors., , , , , , , и . DAC, стр. 486-491. ACM, (2002)A Digitally Controlled Fully Integrated Voltage Regulator With 3-D-TSV-Based On-Die Solenoid Inductor With a Planar Magnetic Core for 3-D-Stacked Die Applications in 14-nm Tri-Gate CMOS., , , , , , , и . IEEE J. Solid State Circuits, 53 (4): 1038-1048 (2018)An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS., , , , , , , , , и 2 other автор(ы). VLSI Circuits, стр. 1-2. IEEE, (2016)Dynamic sleep transistor and body bias for active leakage power control of microprocessors., , , , , и . IEEE J. Solid State Circuits, 38 (11): 1838-1845 (2003)Circuit techniques for dynamic variation tolerance., , , , , , и . DAC, стр. 4-7. ACM, (2009)A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor., , , , , , , , , и 4 other автор(ы). IEEE J. Solid State Circuits, 42 (1): 233-242 (2007)A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS., , , , , , , , , и 5 other автор(ы). IEEE J. Solid State Circuits, 38 (11): 1866-1875 (2003)Formal derivation of optimal active shielding for low-power on-chip buses., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (5): 821-836 (2006)Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques., , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 53-I (9): 1928-1933 (2006)Peak-Current-Controlled Ganged Integrated High-Frequency Buck Voltage Regulators in 22nm CMOS for Robust Cross-Tile Current Sharing., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 262-264. IEEE, (2021)