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Disambiguation of "Shimomura, Naoharu"

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7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.

, , , , , , , , , , , , and . ISSCC, page 132-133. IEEE, (2016)

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7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme., , , , , , , , , and 3 other author(s). ISSCC, page 132-133. IEEE, (2016)7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU., , , , , and . VLSIC, page 1-2. IEEE, (2014)High-Speed Magnetoresistive Random-Access Memory Random Number Generator Using Error-Correcting Code., , , , , and . CoRR, (2016)High-Speed Voltage Control Spintronics Memory (VoCSM) Having Broad Design Windows., , , , , , , , , and 4 other author(s). VLSI Circuits, page 83-84. IEEE, (2018)High-speed voltage-control spintronics memory focused on reduction in write current., , , , , , , , , and 5 other author(s). NVMTS, page 1-5. IEEE, (2017)Temperature dependence of tunnel resistance for CoFeB/MgO/CoFeB magnetoresistive tunneling junctions: The role of magnon, , , , , , , and . 10th JOINT MMM/INTERMAG CONFERENCE, 101 (9): 09B504 (2007)The progresses of MRAM as a memory to save energy consumption and its potential for further reduction., , , , and . VLSIC, page 104-. IEEE, (2015)MRAM Write Error Categorization with QCKB., , , , , , , , , and . MTDT, page 43-48. IEEE Computer Society, (2006)A 64Mb MRAM with clamped-reference and adequate-reference schemes., , , , , , , , , and 6 other author(s). ISSCC, page 258-259. IEEE, (2010)