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Implementation of a custom hardware-accelerator for short-read mapping using Burrows-Wheeler alignment.

, , and . EMBC, page 651-654. IEEE, (2013)

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Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products., and . ICRA, page 3691-3696. IEEE Computer Society, (1998)Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit., , , and . ISCAS, page 3017-3020. IEEE, (2012)Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors., , and . ISVLSI, page 193-198. IEEE Computer Society, (2006)Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs., , , and . ISVLSI, page 46-50. IEEE Computer Society, (2005)CNOT-Measure Quantum Neural Networks., , and . ISMVL, page 186-191. IEEE Computer Society, (2018)Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits., , , and . ISMVL, page 167-172. IEEE Computer Society, (2001)Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition., , and . ISMVL, page 161-167. IEEE Computer Society, (2002)Quaternary Universal-Literal CAM for Cellular Logic Image Processing., , and . ISMVL, page 224-229. IEEE Computer Society, (1996)One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing., , and . ISMVL, page 175-182. IEEE Computer Society, (1997)Bayesian Network for algorithm selection: Real-world hierarchy for nodes reduction., and . iCAST/UMEDIA, page 69-75. IEEE, (2013)