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Disambiguation of "Hariyama, Masanori"

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Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit.

, , , and . ISCAS, page 3017-3020. IEEE, (2012)

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Benchmarks for FPGA-Targeted High-Level-Synthesis., , and . CANDAR, page 232-238. IEEE, (2019)Hardware-oriented succinct-data-structure based on block-size-constrained compression., , and . SoCPaR, page 136-140. IEEE, (2015)Implementation of an FPGA-Oriented Complex Number Computation Library Using Intel OneAPI DPC++., , and . MWSCAS, page 1-4. IEEE, (2022)Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals., , , and . ERSA, page 309-310. CSREA Press, (2008)Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals., , and . ISMVL, page 17. IEEE Computer Society, (2006)Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits., , and . ISVLSI, page 243-248. IEEE Computer Society, (2004)A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment., and . APCCAS, page 1803-1806. IEEE, (2006)A Memory-Bandwidth-Efficient Word2vec Accelerator Using OpenCL for FPGA., , , , , , and . CANDAR Workshops, page 103-108. IEEE, (2019)OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions., , , and . Int. J. Reconfigurable Comput., (2017)Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (12): 2658-2669 (2015)