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ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis.

C. Bai, J. Huang, X. Wei, Y. Ma, S. Li, H. Zheng, B. Yu, and Y. Xie. MICRO, page 268-282. ACM, (2023)

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Hongzhong Wu

Zheng-Zheng Kuang

Jiarong Zheng

Xing Zheng

Zheng Ren-Rong

Other publications of authors with the same name

STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization.F. Wang, G. Luo, G. Sun, J. Zhang, J. Kang, Y. Wang, D. Niu, and H. Zheng. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (5): 864-877 (2021)EPQuant: A Graph Neural Network compression approach based on product quantization.L. Huang, Z. Zhang, Z. Du, S. Li, H. Zheng, Y. Xie, and N. Tan. Neurocomputing, (2022)NPS: A Framework for Accurate Program Sampling Using Graph Neural Network.Y. Fang, Z. Liu, Y. Lu, J. Liu, J. Li, Y. Jin, J. Chen, Y. Chen, H. Zheng, and Y. Xie. CoRR, (2023)TT-GNN: Efficient On-Chip Graph Neural Network Training via Embedding Reformation and Hardware Optimization.Z. Qu, D. Niu, S. Li, H. Zheng, and Y. Xie. MICRO, page 452-464. ACM, (2023)DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving.J. Lin, H. Zheng, Z. Zhu, Z. Zhang, and H. David. ISPASS, page 94-104. IEEE Computer Society, (2007)DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric.M. Gao, C. Delimitrou, D. Niu, K. Malladi, H. Zheng, B. Brennan, and C. Kozyrakis. IEEE Micro, 37 (3): 70-78 (2017)Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio.Z. Du, Y. Guan, T. Guan, D. Niu, N. Tan, X. Yu, H. Zheng, J. Meng, X. Yan, and Y. Xie. ICPADS, page 483-490. IEEE, (2022)Power and Performance Trade-Offs in Contemporary DRAM System Designs for Multicore Processors.H. Zheng, and Z. Zhu. IEEE Trans. Computers, 59 (8): 1033-1046 (2010)Accelerating CPU-based Sparse General Matrix Multiplication with Binary Row Merging.Z. Du, Y. Guan, T. Guan, D. Niu, H. Zheng, and Y. Xie. CoRR, (2022)LazyPIM: Efficient Support for Cache Coherence in Processing-in-Memory Architectures.A. Boroumand, S. Ghose, M. Patel, H. Hassan, B. Lucia, N. Hajinazar, K. Hsieh, K. Malladi, H. Zheng, and O. Mutlu. CoRR, (2017)

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Disambiguation of "Zheng, Hongzhong"

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ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis.

Please choose a person to relate this publication to

Hongzhong Wu

Zheng-Zheng Kuang

Jiarong Zheng

Xing Zheng

Zheng Ren-Rong

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Zheng, Hongzhong"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis.

Please choose a person to relate this publication to

Hongzhong Wu

Zheng-Zheng Kuang

Jiarong Zheng

Xing Zheng

Zheng Ren-Rong

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
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ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis.