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Zero skew clock routing in X-architecture based on an improved greedy matching algorithm.

, , , , and . Integr., 41 (3): 426-438 (2008)

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SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography., , and . ISQED, page 566-571. IEEE, (2013)SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips., , , , and . ISPD, page 49-56. ACM, (2015)A thermal-driven force-directed floorplanning algorithm for 3D ICs., , , and . CAD/Graphics, page 497-502. IEEE, (2009)Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs., , , and . ASP-DAC, page 582-587. IEEE, (2006)Efficient model reduction of interconnects via double gramians approximation., , , and . ASP-DAC, page 25-30. IEEE, (2010)Optimization of via distribution and stacked via in multi-layered P/G networks., , and . Integr., 43 (3): 318-325 (2010)Temperature-Aware Electromigration Analysis with Current-Tracking in Power Grid Networks., , and . J. Comput. Sci. Technol., 36 (5): 1133-1144 (2021)Intelligent and kernelized placement: A survey., , and . Integr., (2022)Parallelizing SAT-based de-camouflaging attacks by circuit partitioning and conflict avoiding., , , and . Integr., (2019)UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing., , , , , , and . ASP-DAC, page 834-839. ACM, (2003)