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Disambiguation of "Umanesan, Ganesan"

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Adjacent Double Bit Error Correcting Codes with Single Byte Error Detecting Capability for Memory Systems.

, and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A (2): 490-496 (2002)

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Kathirvel Ganesan

Jayanthi Ganesan

Sundar Ganesan

Sashikumaar Ganesan

Jayavarshni Ganesan

 

Other publications of authors with the same name

The SAGE Project: a Storage Centric Approach for Exascale Computing., , , , , , , , , and 1 other author(s). CoRR, (2018)SAGE: Percipient Storage for Exascale Data Centric Computing., , , , , , , , , and . CoRR, (2018)NoaSci: A Numerical Object Array Library for I/O of Scientific Applications on Object Storage., , , , , , , , and . PDP, page 172-176. IEEE, (2022)Single Byte Error Control Codes with Double Bit within a Block Error Correcting Capability for Semiconductor Memory Systems., and . DFT, page 192-200. IEEE Computer Society, (2000)A Class of Random Multiple Bits in a Byte Error Correcting and Single Byte Error Detecting (S_t/b EC-S_bED) Codes., and . IEEE Trans. Computers, 52 (7): 835-847 (2003)Single Byte Error Correcting Codes with Double Bit within a Block Error Correcting Capability for Memory Systems., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A (2): 513-517 (2002)Adjacent Double Bit Error Correcting Codes with Single Byte Error Detecting Capability for Memory Systems., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A (2): 490-496 (2002)Parallel Decoding Cyclic Burst Error Correcting Codes., and . IEEE Trans. Computers, 54 (1): 87-92 (2005)Random Double Bit Error Correcting-Single b-bit Byte Error Correcting (DEC-SbEC) Codes for Memory Systems., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A (1): 273-276 (2002)A Class of Random Multiple Bits in a Byte Error Correcting (S t/b EC)Codes for Semiconductor Memory Systems., and . PRDC, page 247-256. IEEE Computer Society, (2002)