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Disambiguation of "Ohno, Hideo"

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Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure.

, , , , , , , , , , and . VLSIC, page 172-. IEEE, (2015)

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Herbert Ohno

Masataka Ohno

Hideo Baba

Terufumi Ohno

Hideo Ohashi

 

Other publications of authors with the same name

Dependence of Giant Tunnel Magnetoresistance of Sputtered CoFeB/MgO/CoFeB Magnetic Tunnel Junctions on MgO Barrier Thickness and Annealing Temperature, , , , and . Japanese Journal of Applied Physics, 44 (19): 587-589 (2005)On sensor image compression., , , , , , and . IEEE Trans. Circuits Syst. Video Technol., 7 (3): 543-548 (1997)A full-stack view of probabilistic computing with p-bits: devices, architectures and algorithms., , , , , , , , , and 2 other author(s). CoRR, (2023)Double-Free-Layer Stochastic Magnetic Tunnel Junctions with Synthetic Antiferromagnets., , , , , and . CoRR, (2023)A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing., , , , , , , , , and 5 other author(s). ISCAS, page 1588-1591. IEEE, (2014)A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 54 (11): 2991-3004 (2019)Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits., , , , , , , , and . IEICE Trans. Electron., 93-C (5): 608-613 (2010)An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (2): 109-119 (2016)Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme., , , , , , and . ASP-DAC, page 475-476. IEEE, (2012)Integer factorization using stochastic magnetic tunnel junctions., , , , , and . Nat., 573 (7774): 390-393 (2019)