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A Test Vector Inhibiting Technique for Low Energy BIST Design.

P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch. VTS, page 407-412. IEEE Computer Society, (1999)

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Benoît Girard

Adrien Girard

Jules Girard

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Yann Girard

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Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments.A. Yan, Z. Li, J. Cui, Z. Huang, T. Ni, P. Girard, and X. Wen. IEEE Trans. Aerosp. Electron. Syst., 59 (3): 2885-2897 (June 2023)A Ring Architecture Strategy for BIST Test Pattern Generation.C. Fagot, O. Gascuel, P. Girard, and C. Landrault. J. Electron. Test., 19 (3): 223-231 (2003)Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata.A. Yan, R. Liu, J. Cui, T. Ni, P. Girard, X. Wen, and J. Zhang. IEEE Trans. Circuits Syst. II Express Briefs, 70 (6): 2256-2260 (June 2023)Emerging Computing Devices: Challenges and Opportunities for Test and Reliability*.A. Bosio, I. O'Connor, M. Traiola, J. Echavarria, J. Teich, M. Hanif, M. Shafique, S. Hamdioui, B. Deveautour, P. Girard and 2 other author(s). ETS, page 1-10. IEEE, (2021)Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications.A. Yan, Z. Xu, J. Cui, Z. Ying, Z. Huang, H. Liang, P. Girard, and X. Wen. ISCAS, page 1-5. IEEE, (2020)A Low Overhead and Double-Node-Upset Self-Recoverable Latch.A. Yan, F. Xia, T. Ni, J. Cui, Z. Huang, P. Girard, and X. Wen. ITC-Asia, page 1-5. IEEE, (2023)Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS.A. Yan, S. Song, J. Zhang, J. Cui, Z. Huang, T. Ni, X. Wen, and P. Girard. ITC-Asia, page 73-78. IEEE, (2022)Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits.N. Gupta, N. Agrawal, N. Dhakad, A. Shah, S. Vishvakarma, and P. Girard. ACM Great Lakes Symposium on VLSI, page 307-312. ACM, (2021)Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications.A. Yan, Z. He, J. Xiang, J. Cui, Y. Zhou, Z. Huang, P. Girard, and X. Wen. ACM Great Lakes Symposium on VLSI, page 261-266. ACM, (2022)A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology.A. Yan, Z. Zhou, S. Wei, J. Cui, Y. Zhou, T. Ni, P. Girard, and X. Wen. ACM Great Lakes Symposium on VLSI, page 255-260. ACM, (2022)

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Disambiguation of "Girard, Patrick"

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A Test Vector Inhibiting Technique for Low Energy BIST Design.

Please choose a person to relate this publication to

Benoît Girard

Adrien Girard

Jules Girard

Pierre Girard

Yann Girard

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Girard, Patrick"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Test Vector Inhibiting Technique for Low Energy BIST Design.

Please choose a person to relate this publication to

Benoît Girard

Adrien Girard

Jules Girard

Pierre Girard

Yann Girard

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A Test Vector Inhibiting Technique for Low Energy BIST Design.