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A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process., , , , и . ASP-DAC, стр. 89-90. IEEE, (2013)Low Power Cache with Successive Tag Comparison Algorithm., , , и . PATMOS, том 2799 из Lecture Notes in Computer Science, стр. 599-606. Springer, (2003)A 5-Bit 500-MS/S Flash ADC using Time-Domain Comparison., , , , и . Journal of Circuits, Systems, and Computers, (2012)An on-chip soft-start technique of current-mode DC-DC converter for biomedical applications., , , и . APCCAS, стр. 500-503. IEEE, (2010)A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC., , , , , и . ISSCC, стр. 184-595. IEEE, (2007)A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE., , , и . VLSI Circuits, стр. 1-2. IEEE, (2016)A 32-Gb/s Dual-Mode Transceiver With One-Tap FIR and Two-Tap IIR RX Only Equalization in 65-nm CMOS Technology., , и . IEEE Trans. Very Large Scale Integr. Syst., 29 (8): 1567-1574 (2021)A 1.62 Gb/s-2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection., , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (2): 268-278 (2013)Survey and Analysis of Delay-Locked Loops Used in DRAM Interfaces., и . IEEE Trans. Very Large Scale Integr. Syst., 22 (4): 701-711 (2014)A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time., , , и . IEEE Trans. Very Large Scale Integr. Syst., 17 (10): 1461-1469 (2009)