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Disambiguation of "Choi, Young-Jung"

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A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC.

, , , , , and . ISSCC, page 184-595. IEEE, (2007)

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Young Jung

Se-Young Choi

Young-Soon Choi

Jin-Young Choi

Won-Young Choi

 

Other publications of authors with the same name

A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface., , , , , , , , , and 6 other author(s). ISCAS, page 3861-3864. IEEE, (2010)A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL., , , , , , , , , and 3 other author(s). ISSCC, page 547-556. IEEE, (2006)A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 42 (11): 2369-2377 (2007)A Fast-lock Synchronous Multi-phase Clock Generator based on a Time-to-digital Converter., , , , and . ISCAS, page 1-4. IEEE, (2009)An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface., , , , , , , and . ISSCC, page 312-313. IEEE, (2013)A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface., , , , , , , , , and 1 other author(s). ISSCC, page 48-50. IEEE, (2012)A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS., , , , , , , , , and 14 other author(s). ISSCC, page 140-141. IEEE, (2009)SDTV Quality Assessment Using Energy Distribution of DCT Coefficients., , , , and . ICESS, page 118-125. IEEE Computer Society, (2008)A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology., , , , , , , , , and 12 other author(s). ISSCC, page 282-283. IEEE, (2008)A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology., , , , , , , , and . IEEE J. Solid State Circuits, 47 (1): 131-140 (2012)