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A formal model for proving hardware timing properties and identifying timing channels.

, , , , and . Integr., (2020)

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NEMTronics: Symbiotic integration of nanoelectronic and nanomechanical devices for energy-efficient adaptive computing., , , and . NANOARCH, page 210-217. IEEE Computer Society, (2011)SACCI: Scan-Based Characterization Through Clock Phase Sweep for Counterfeit Chip Detection., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (5): 831-841 (2015)Sequential hardware Trojan: Side-channel aware design and placement., , , , and . ICCD, page 297-300. IEEE Computer Society, (2011)Role of power grid in side channel attack and power-grid-aware secure design., , , , , , , and . DAC, page 78:1-78:9. ACM, (2013)Hardware Trojan attacks in embedded memory., , , , and . VTS, page 1-6. IEEE Computer Society, (2018)Content Delivery for High-Speed Railway via Integrated Terrestrial-Satellite Networks., , , , and . WCNC, page 1-6. IEEE, (2020)Property specific information flow analysis for hardware security verification., , , , and . ICCAD, page 89. ACM, (2018)Security Path Verification Through Joint Information Flow Analysis., , and . APCCAS, page 415-418. IEEE, (2018)Leveraging Unspecified Functionality in Obfuscated Hardware for Trojan and Fault Attacks., , , and . AsianHOST, page 1-6. IEEE, (2019)Golden-Free Hardware Trojan Detection with High Sensitivity Under Process Noise., , , , and . J. Electron. Test., 33 (1): 107-124 (2017)