( en | de | ru )

 

Disambiguation of "Garlepp, Bruno W."

Author of the publication

copydeleteadd this publication to your clipboard
1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus.

, , , , , , and . IEEE J. Solid State Circuits, 36 (5): 752-760 (2001)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Christoph Garlepp

Bruno W Neu

Paul W Bruno

Bruno W Nikles

Dieter Garlepp

 

Other publications of authors with the same name

A new technique for characterization of digital-to-analog converters in high-speed systems., , , , and . DATE, page 433-438. EDA Consortium, San Jose, CA, USA, (2007)A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 41 (12): 2930-2944 (2006)A 2.5Gb/s Multi-Rate 0.25µm CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter., , , , , and . ISSCC, page 1276-1285. IEEE, (2006)A portable digital DLL for high-speed CMOS interface circuits., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 34 (5): 632-644 (1999)1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus., , , , , , and . IEEE J. Solid State Circuits, 36 (5): 752-760 (2001)A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillator., , , , , , , , , and 1 other author(s). ISSCC, page 244-245. IEEE, (2010)Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 40 (4): 1012-1026 (2005)A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter., , , , , , , and . IEEE J. Solid State Circuits, 43 (4): 999-1009 (2008)A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 45 (12): 2566-2581 (2010)A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications., , , , and . IEEE J. Solid State Circuits, 43 (5): 1207-1216 (2008)