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Pathfinding: A design methodology for fast exploration and optimisation of 3D-stacked integrated circuits.

, , , and . SoC, page 118-123. IEEE, (2009)

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Holistic pathfinding: virtual wireless chip design for advanced technology and design exploration., , , and . DAC, page 593. ACM, (2008)Simulation methodology and flow integration for 3D IC stress management., , , , , and . CICC, page 1-4. IEEE, (2010)Variation-aware analysis: savior of the nanometer era?, , , , , and . DAC, page 411-412. ACM, (2006)Are there economic benefits in DFM?, and . DAC, page 767-768. ACM, (2005)Roadmap for design and EDA infrastructure for 3D products.. Hot Chips Symposium, page 1-21. IEEE, (2012)Power and signal integrity challenges in 3D systems., , , , , and . DAC, page 161:1-161:4. ACM, (2013)Integration of CMP Modeling in RC Extraction and Timing Flow., , , and . CICC, page 249-252. IEEE, (2007)Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study., , , , , , , , and . 3DIC, page 1-6. IEEE, (2009)Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs., , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (1): 186-191 (2012)Moore's Law: another casualty of the financial meltdown?, , , , , , , , and . DAC, page 202-203. ACM, (2009)