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A dynamic binary translation approach to architectural simulation.

, , and . SIGARCH Comput. Archit. News, 29 (1): 27-36 (2001)

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Constraint Graph Analysis of Multithreaded Programs., , and . J. Instruction-Level Parallelism, (2004)Energy-Efficient Bayesian Inference Using Bitstream Computing., , and . IEEE Comput. Archit. Lett., 22 (1): 37-40 (January 2023)SHASTA: Synergic HW-SW Architecture for Spatio-temporal Approximation., , and . ACM Trans. Archit. Code Optim., 17 (4): 25:1-25:26 (2020)Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing., , , , and . MICRO, page 328-337. ACM/IEEE Computer Society, (2001)Combating Aging with the Colt Duty Cycle Equalizer., , , and . MICRO, page 103-114. IEEE Computer Society, (2010)Implementing Optimizations at Decode Time., and . ISCA, page 221-232. IEEE Computer Society, (2002)Memory Ordering: A Value-Based Approach., and . ISCA, page 90-101. IEEE Computer Society, (2004)CHARSTAR: Clock Hierarchy Aware Resource Scaling in Tiled ARchitectures., and . ISCA, page 147-160. ACM, (2017)Circuit-Switched Coherence., , and . NOCS, page 193-202. IEEE Computer Society, (2008)TailWAG: Tail Latency Workload Analysis and Generation., and . BID@PPOPP, page 1:1-1:9. ACM, (2023)