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Universal Testing for Linear Feed-Forward/Feedback Shift Registers.

, , and . IEICE Trans. Inf. Syst., 103-D (5): 1023-1030 (2020)

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The Complexity of Fault Detection Problems for Combinational Logic Circuits., and . IEEE Trans. Computers, 31 (6): 555-560 (1982)Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints., , , , , and . J. Electron. Test., 28 (4): 511-521 (2012)Effect of BIST Pretest on IC Defect Level., , and . IEICE Trans. Inf. Syst., 89-D (10): 2626-2636 (2006)Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers., and . IEICE Trans. Inf. Syst., 98-D (10): 1852-1855 (2015)A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification., , and . IEICE Trans. Inf. Syst., 93-D (7): 1857-1865 (2010)Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design., , and . IEICE Trans. Inf. Syst., 94-D (7): 1430-1439 (2011)A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips., , and . IEICE Trans. Inf. Syst., 89-D (4): 1490-1497 (2006)Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents., and . IEICE Trans. Inf. Syst., 100-D (9): 2232-2236 (2017)Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints., , , and . IEICE Trans. Inf. Syst., 91-D (3): 807-814 (2008)Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability., , , and . IEICE Trans. Inf. Syst., 90-D (1): 296-305 (2007)