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The Coming Wave of Multithreaded Chip Multiprocessors., and . Int. J. Parallel Program., 35 (3): 299-330 (2007)The RASE (Rapid, Accurate Simulation Environment) for chip multiprocessors., , and . SIGARCH Comput. Archit. News, 33 (4): 14-23 (2005)GiPH: Generalizable Placement Learning for Adaptive Heterogeneous Computing., , , , , , , , and . CoRR, (2023)Fair Queuing Memory Systems., , , and . MICRO, page 208-222. IEEE Computer Society, (2006)Towards the Co-design of Neural Networks and Accelerators., , , , , , , , , and . MLSys, mlsys.org, (2022)A Transferable Approach for Partitioning Machine Learning Models on Multi-Chip-Modules., , , , , , , , and . MLSys, mlsys.org, (2022)Ten Lessons From Three Generations Shaped Google's TPUv4i : Industrial Product., , , , , , , , , and 6 other author(s). ISCA, page 1-14. IEEE, (2021)Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors., , , , , and . ISCA, page 15-26. ACM, (1990)Architectural and implementation tradeoffs in the design of multiple-context processors., , and . ISCA, page 435. ACM, (1992)The DASH Prototype: Implementation and Performance., , , , , , and . 25 Years ISCA: Retrospectives and Reprints, page 418-429. ACM, (1998)