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Disambiguation of "Nauta, Bram"

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A 100-800 MHz 8-Path Polyphase Transmitter With Mixer Duty-Cycle Control Achieving <-40 dBc for ALL Harmonics.

, , , , and . IEEE J. Solid State Circuits, 49 (3): 595-607 (2014)

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Walther Arnold Nauta

Michael Nauta

Bram Hanse

Bram Bolder

Bram Eldering

 

Other publications of authors with the same name

Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers., , and . ISCAS, page 2854-2857. IEEE, (2007)On the Suitability of Discrete-Time Receivers for Software-Defined Radio., , and . ISCAS, page 2522-2525. IEEE, (2007)A multi-step P-cell for LNA design automation., , and . ISCAS, page 2550-2553. IEEE, (2008)A wideband IM3 cancellation technique for CMOS attenuators., , , , and . ISSCC, page 78-80. IEEE, (2012)Introduction to the Special Issue on the 41st European Solid-State Circuits Conference (ESSCIRC)., , and . IEEE J. Solid State Circuits, 51 (7): 1511-1513 (2016)A 10-bit Charge-Redistribution ADC Consuming 1.9 μ W at 1 MS/s., , , , , and . IEEE J. Solid State Circuits, 45 (5): 1007-1015 (2010)A 100-800 MHz 8-Path Polyphase Transmitter With Mixer Duty-Cycle Control Achieving <-40 dBc for ALL Harmonics., , , , and . IEEE J. Solid State Circuits, 49 (3): 595-607 (2014)Enhanced-Selectivity High-Linearity Low-Noise Mixer-First Receiver With Complex Pole Pair Due to Capacitive Positive Feedback., , , , and . IEEE J. Solid State Circuits, 53 (5): 1348-1360 (2018)Compact Cascadable g m -C All-Pass True Time Delay Cell With Reduced Delay Variation Over Frequency., , , and . IEEE J. Solid State Circuits, 50 (3): 693-703 (2015)A Fully Passive RF Front End With 13-dB Gain Exploiting Implicit Capacitive Stacking in a Bottom-Plate N-Path Filter/Mixer., , , and . IEEE J. Solid State Circuits, 55 (5): 1139-1150 (2020)