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A Deep Neural Network Guided Testing Approach for Finite State Machines., , and . ISDCS, page 1-6. IEEE, (2021)A Combinational Logic Mapper for Actel's SX/AX Family., and . VLSI Design, page 669-672. IEEE Computer Society, (2005)Low Power Technology Mapping for LUT based FPGA Ä Genetic Algorithm Approach"., and . VLSI Design, page 79-84. IEEE Computer Society, (2003)Genetic Algorithm based Approach for Low Power Combinational Circuit Testing., and . VLSI Design, page 552-. IEEE Computer Society, (2003)Synthesis of Finite State Machines for Low Power and Testability., , and . APCCAS, page 1434-1437. IEEE, (2006)Three-level AND-OR-XOR network synthesis: A GA based approach., , and . APCCAS, page 574-577. IEEE, (2008)A hardware based low temperature solution for VLSI testing using decompressor side masking., , , and . ISCAS, page 637-640. IEEE, (2015)An ATE assisted DFD technique for volume diagnosis of scan chains., , , and . DAC, page 31:1-31:6. ACM, (2013)Fault Coverage Enhancement via Weighted Random Pattern Generation in BIST Using a DNN-Driven-PSO Approach., , , , , and . ICIT, page 228-233. IEEE, (2019)Low power finite state machine synthesis using power-gating., , and . Integr., 44 (3): 175-184 (2011)